1. Field of the Invention
This invention relates to a semiconductor memory. In particular, the invention relates to the connection of the bit lines and the restore circuits in a memory which has barrier transistors between the bit lines and the sense amplifiers.
2. Description of the Related Art
As shown in FIG. 1, in conventional memories of this type, for instance the dynamic RAM (random access memory), barrier transistors T1 and T2 formed by N channel MOS transistors are inserted at one end of the bit line pair BL and BL of each column in the memory cell array 3. Restore circuit 1 and synchronized sense amplifier 2 are connected to the bit line pair section on the opposite side of the memory cell array 3 using barrier transistors T1 and T2 as a reference. This sense amplifier 2 operates the sense amplification and latch action by receiving synchronization signal .phi.1. A dummy cell circuit 4 and precharge equalizer circuit 5 are connected in series to the other end of the bit line pair BL and BL.
As is well known, for reading the memory cell data in a dynamic RAM, sense amplifier 2 reads the slight difference in potential which is generated in the bit line pair BL and BL by amplifying it and determines data "1" or "0". However, a problem arises in that the more the integration of dynamic RAMs progresses, the greater becomes the load capacity of bit lines BL and BL and the longer the sensing time becomes. Therefore, to counteract this, a resistance component due to the barrier transistors T1 and T2 is inserted between bit lines BL and BL and sense amplifier 2 so that latching of the bit line potential by sense amplifier 2 is made faster.
A barrier control signal .phi.T is applied to the gates of barrier transistors T1 and T2. The potentials shown in the following Table are used for this signal .phi.T according to the bit line precharge system.
______________________________________ Bit line precharge potential Sensing Restoring Precharging ______________________________________ Vcc (Power source potential) &gt;Vcc + VT &gt;Vcc + VT &gt;Vcc + VT Vss (Earth potential) Vcc &gt;Vcc + VT Vcc Vcc/2 Vcc &gt;Vcc + VT Vcc ______________________________________
Here, VT is the threshold voltage of barrier transistors T1 and T2. Accordingly, when restoring, it is necessary to make the bit line potential Vcc. Thus, at this time, in order to set barrier transistors T1 and T2 to the ON state, each system requires a greater potential than (Vcc+VT) as the .phi.T potential. In this case, in the Vss precharge system and the Vcc/2 system, it is necessary to step up the potential so that .phi.T is .gtoreq.Vcc+VT during restoring, which is different from other periods.
In the conventional memories mentioned above, a voltage step-up circuit (not shown in the FIG. is required as a memory peripheral circuit in order to generate the control signal .phi.T. This leads to accompanying problems in that the design and construction are more complicated, the area occupied on the memory clip surface is increased and, consequently, the area of the memory chip is increased.